A system on chip (SOC) integrated circuit (IC) can require a supply voltage and well bias voltage to operate the transistors on the SOC. Well biasing is used, for example, to maintain the well voltage of a p-channel metal-oxide semiconductor (PMOS) transistor at a potential that exceeds its source voltage. This enables low-power modes of SOC operation (i.e., low power run modes) by increasing the transistor's threshold voltage and, thereby, reducing its sub-threshold leakage.
To enable proper transistor biasing during low-power run modes of the SOC, the difference or delta between the well bias voltage and the supply voltage should remain constant; otherwise timing issues may arise. During low-power run modes, the supply voltage can be noisy, and it is challenging to design a voltage regulator that produces a well bias voltage that tracks or follows the supply voltage under these conditions. An additional consideration is that any power used to create the well bias voltage reduces the efficiency of well biasing. Therefore, a low-power method of creating the well bias voltage is desirable.